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Posted: Wednesday, January 31, 2018 12:07 PM

You will be part of the world class SoC physical Integration and Design team within the Scalable Performance CPU Development Group SDG working on next generation Xeon Server CPUs

Your responsibilities will include but not be limited to:

  • Timing convergence at the SoC level, hierarchical design planning and path clearing of complex integrated circuits and blocks.
  • Performs all aspects of the SoC design flow from high-level design planning of assembly levels, floor-planning to synthesis, place and route, timing and power and other backend electrical verification tools to create a design database that is ready for manufacturing.
  • This position requires expertise in Static Timing Analysis and expertise in Synopsys PrimeTime tool usage to analyze complex timing problems, triage and come up with timing fixes, ability to drive timing convergence at the assembly level of hierarchy or SoC.

The ideal candidate will be able to demonstrate the following behaviors:

  • Ability to work independently and at various levels of abstraction
  • Strong analytical ability and problem solving skills
  • Ability to work effectively with both internal and external teams/customers is expected.
  • Strong written and verbal communication skills
  • Ability to mentor other engineers and technically guide them.
  • Capable of working in a high performing team to deliver the results required from the organization.
  • Facilitator of direct and open communication, diversity of opinion, and debate.

Minimum Qualifications:

BS degree in Electrical Engineering, Computer Engineering or other related field of study with a minimum of 8+ years of relevant experience in SOC/IP physical design or MS degree with 5+ years or PHD with 5+ years of direct related experience with SOC Physical design and Static Timing Analysis


Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

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• Location: Akron/Canton, Hudson

• Post ID: 57819702 akroncanton is an interactive computer service that enables access by multiple users and should not be treated as the publisher or speaker of any information provided by another information content provider. © 2018