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Posted: Thursday, January 25, 2018 2:07 AM

This is an excellent opportunity for a creative and motivated engineer to be part of Scalable Performance CPU Development Group (SDG) team doing exciting work in the development of next generation server Xeon microprocessors. This role offers a platform for the engineer to take his/her logic design skills to a whole new level. You will be responsible for the following:

  • Define microarchitecture and write IP specifications
  • Implement design in RTL
  • Collaborate with pre-silicon validation team to develop functional test plans
  • Collaborate with post-silicon to resolve silicon level sightings
  • Collaborate with physical design team on floor planning and timing closure

This position is located in Hudson, MA.


Qualifications: You must possess Minimum Qualifications (listed below) to be initially considered for this position. Preferred Qualifications (listed below) are in addition to the minimum qualifications are considered a plus factor in identifying top candidates. Minimum Qualifications: BS or MS degree in Electrical or Computer Engineering or related fields 5+ years of overall experience performing RTL logic design using System Verilog Experience in the past 4+ years with design partitioning, micro-architecture trade-offs , and high speed digital logic design (including timing closure Experience in the past 4+ years working with validation engineers to develop functional validation and coverage test plans Experience in the past 4+ years with multi-power domains and multi-clock designs Strong problem solving and debugging skills and ability to work closely with various chip design disciplines and cross site teams Proven verbal and written communication skills Motivated, self-directed, and able to work effectively both independently and in a team environment Preferred Qualifications: Experience in Design for Test (DFT) and Design for Debug (DFD) in a large chip development environment Ability to debug errors in various cad tools (Synopsys SOC IP integration tools (coreBuilder, coreAssembler, vcs, etc.) Good level of understanding of the power Management, reset, clock, and power domain challenges for large SoCs Experience dealing with Inter IP floor planning and timing, ability to work closely with Physical designers

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

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• Location: Akron/Canton

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